1. Field of the Invention
The present invention relates in general to semiconductor memories, and in particular, to apparatus and method for correcting duty cycle of clock signals used in semiconductor memories.
2. Background of the Invention
Conventional duty cycle correction (DCC) technology can be classified into analogue DCC and digital DCC. Analogue DCC implementations tend to suffer from larger static current and narrower correction range for the duty cycle. On the other hand, analogue DCC typically provides higher resolution and therefore higher degree of correction, and are comparatively smaller in circuit size. In contrast, the drawbacks of the digital DCC are larger size and difficulty in significantly improving resolution. Moreover, digital DCC has a further disadvantage in that it is susceptible to noises occurring in the power supply. However, digital DCC merits are that it its static current is low, the correction process is rapid, and the correction range is wide. Due to such advantages, the digital DCC has been preferably utilized to correct clock signal duty cycle in semiconductor memory devices.
One type of digital DCC is disclosed in commonly owned copending application, U.S. Ser. No. 10/331,412, filed on Dec. 30, 2002, entitled “DIGITAL DLL APPARATUS FOR CORRECTING DUTY CYCLE AND METHOD THEREOF”, which is incorporated herein by reference. In such digital DCC, two delay lock loops (DLLs) are provided for the duty cycle correction. Because the DLL circuitry is nearly doubled in size (two phase mixers, two delay model units and two direct phase detectors), this implementation consumes larger silicon area.
Further, precise synchronization requires each of the two phase mixers, the two delay model units and the two direct phase detectors in each of the two delay lock loops to have substantially identical delay regardless of variations in process, voltage, temperature, etc. In such digital DCC, however, it is a challenge to match the phases of the two clocks used for each of the two delay lock loops accurately by equalizing each delay amount of the circuit elements, i.e., the phase mixers, the delay model units and the second direct phase detectors, involved in each delay lock loop.